代表论著：
[1] Zhu, Haozhe, Bo Jiao, Jinshan Zhang et al. “COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning”, In 2022 International Solid-State Circuits Conference (ISSCC), pp. 250-252, IEEE, 2022.
[2] Zhu, Haozhe, Chixiao Chen, Shiwei Liu et al. “A Communication-Aware DNN Accelerator on ImageNet Using in-Memory Entry-Counting Based Algorithm-Circuit-Architecture Co-Design in 65nm CMOS.” In IEEE Journal on Emerging and Selected Topics in Circuits and Systems10, no. 3 (2020): 283-294.
[3] Zhu, Haozhe, Yu Wang, and C.-J. Richard Shi. “Tanji: A General-Purpose Neural Network Accelerator with a Unified Crossbar Architecture.”IEEE Design & Test37, no. 1 (2019): 56-63.
[4] Jiao, Bo, Haozhe Zhu, Jinshan Zhang et al. “Computing Utilization Enhancement for Chiplet-based Homogeneous Processing-in-Memory Deep Learning Processors.” In 2021 31st Great Lakes Symposium on VLSI (GLSVLSI), pp. 241-246. ACM, 2021. (Co-first author)
[5] Jia, Xinru, Haozhe Zhu et al. “Accepted, not yet officially published”, In2022 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, 2022.
[6] Zhang, Jinshan, Bo Jiao, Yunzhengmao Wang,Haozhe Zhuet al. “ALPINE: An Agile Processing-in-Memory Macro Compilation Framework.” In2021 31st Great Lakes Symposium on VLSI (GLSVLSI), pp. 333-338. ACM, 2021.
[7] Liu, Shiwei, Haozhe Zhu, Chixiao Chen et al. “XNORAM: An Efficient Computing-in-Memory Architecture for Binary Convolutional Neural Networks with Flexible Dataflow Mapping.” In2020 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), pp. 21-25. IEEE, 2020.
