陈迟晓，bwin必赢副研究员、上海市青年科技启明星。2010年，2015年分别获得bwin必赢微电子学士和博士学位，本科期间在美国UC Davis大学交流一年，攻读博士期间获得ISSCC STGA奖，bwin必赢优秀博士研究奖。2016—2018年，在美国华盛顿大学电子工程系的开展博士后研究。2019年起，加入bwin必赢工程与应用技术研究院、专用集成电路国家重点实验室。2021年，转入bwin必赢bwin必赢。主持国家自然科学基金委面上项目等。主要研究领域包括面向AI芯片的算法-电路-架构协同设计、感存算一体电路与架构、数模混合集成电路及开源EDA方法，Chiplet异质异构集成。以第一、通信作者发表多篇集成电路设计领域论文，包括DAC、ESSCIRC、ASP-DAC、ISCAS、GLSVLSI、MWSCAS、AICAS、IEEE TCAS-I/II、IEEE JETCAS等。教科研研之余积极推动半导体领域科普，是知名半导体公众号“矽说”的共同创始人与主笔。

1. B. Yu, C. Chen, et al., “A 14-bit 200-MS/s time-interleaved ADC with sample-time      error detection

   and cancelation,” IEEE Asian Solid-State Circuits      Conference (ASSCC) 2011, Jeju, 2011, pp. 349-352.

2. C. Chen, et al., “A low-offset calibration-free comparator with a      mismatch-suppressed dynamic

   preamplifier,” 2014 IEEE International      Symposium on Circuits and Systems (ISCAS), Melbourne VIC,

   2014, pp.      2361-2364.

3. C. Chen, et al., “An ARMA-Model-Based NTF Estimation on Continuous-Time      Sigma-Delta

   Modulators,” in IEEE Transactions on Circuits and Systems II:      Express Briefs, vol. 62, no. 8, pp. 721

   725, Aug. 2015.

4. C. Chen, et al., “OCEAN: An on-chip incremental-learning enhanced processor      with gated recurrent

   neural network accelerators,” IEEE European Solid      State Circuits Conference (ESSCIRC), Leuven,

   2017, pp. 259-262.

5. C. Chen, et al., “iFPNA: A Flexible and Efficient Deep Neural Network      Accelerator with a

   Programmable Data Flow Engine in 28nm CMOS,” IEEE 44th      European Solid State Circuits

   Conference (ESSCIRC), Dresden, 2018, pp.      170-173.

6. C. Chen, et al., “Exploring the Programmability for Deep Learning      Processors: from Architecture to

   Tensorization,” ACM/ESDA/IEEE Design      Automation Conference (DAC), San Francisco, CA, 2018, pp.

   1-6.

7. A. Wang, C. Chen and C. R. Shi, “A 9-bit Resistor-Based All-Digital      Temperature Sensor with a SAR

   Quantization Embedded Differential Low-Pass      Filter in 65nm CMOS Consuming 57pJ with a 2.5 us

   Conversion Time”, Custom      Integrated Circuit Conference (CICC 2019), Austin, TX, April 2019.

8. T. Zhang, Y. Cao, S. Zhang,C. Chen, F. Ye and J. Ren, “Machine Learning Based Prior-Knowledge-Free

   Calibration for Split Pipelined-SAR ADCs with Open-Loop Amplifiers Achieving 93.7-dB SFDR”, ESSCIRC

   2019, Krakow pp.189-192. 

9. H. Zhu, C. Chen, et al., “A Communication-Aware DNN Accelerator on ImageNet Using      in-Memory

   Entry-Counting Based Algorithm-Circuit-Architecture Co-Design in      65nm CMOS,” in IEEE Journal on

   Emerging and Selected Topics in Circuits      and System, vol. 10, no. 3, pp. 283-294, Sept. 2020.

10. B. Jiao, et al., and C. Chen.“Computing Utilization Enhancement for Chiplet-based Homogeneous

    Processing-in-Memory Deep Learning Processors”, ACM Great Lakes Symposium on VLSI (GLSVLSI),

    2021.